1. Field of the Invention
This invention relates to technologies for packaging semiconductor chips, and more particularly, to a method for packaging semiconductor chips based on a lead-on-chip (LOC) architecture which allows the size of the IC package to be substantially close to the chip size so as to reduce the packaging size to the minimum.
2. Description of Related Art
In the semiconductor industry, the objective of making the IC packages as small as possible is always a primary concern. Related technologies include the small outline package (SOP), the small J-lead package (SOJ), the thin small outline package (TSOP), and so on. These technologies are all based on a lead-on-chip (LOC) architecture which allows the packaging to be made with a smaller molding compound encapsulating the semiconductor chip. The overall size of the IC package can thus be made as small as close to the chip size.
However, the SOP, SOJ, and even the TSOP architecture still use the transfer molding technology for the encapsulation. If a molding compound is to be made very thin, the channel therein for directing epoxy is correspondingly small. As a consequence, the molding compound can hardly made to a thickness less than 1.0 mm. Furthermore, with small channels forceful thrust is required to flow the epoxy through the channels. This could cause the die paddles to be shifted in such manners as to cause the bonding wires to be exposed to the outside of the molding compound or to cause them to be displaced and thus short-circuited.
In packaging a semiconductor chip, a leadframe having a plurality of leads thereon is used to support the semiconductor chip. A plurality of bonding wires, typically gold wires, are then used to interconnect the leads on the leadframe to the bonding pads on the semiconductor chip. In conventional types of packaging, the leads are drawn out of the molding compound from the lateral sides, which causes the footprint area of the IC package to be larger than the molding compound. Even though current technologies can make the molding compound very small, the laterally extended leads still cause the overall IC package to take up a large footprint area.
Solutions to the foregoing problem include a chip-on-lead (COL) type of package disclosed in U.S. Pat. No. 5,428,248, an LOC type of package disclosed in U.S. Pat. No. 5,363,279, and another COL type of package disclosed in U.S. Pat. No. 5,430,500. The COL types of packages, in particular, draw the leads out of the molding compound from the bottom side so as to reduce the overall footprint area of the IC package. However, these technologies notwithstanding utilize the transfer molding technology for encapsulation of semiconductor chips. The aforementioned drawbacks still exist in these types of packages.